1. Technical Field
The present invention relates to a delay-locked loop circuit using a phase inversion locking algorithm and a method of controlling the same and, more particularly, to a delay-locked loop circuit capable of implementing a wide operating frequency range, a short locking time, low power consumption, a small chip area, and improved jitter performance by reducing the number of delay units within a digitally-controlled delay line by half to a maximum extent by applying a phase inversion locking algorithm to the delay-locked loop circuit and a method of controlling the delay-locked loop circuit.
2. Description of the Related Art
In order to improve power consumption and the data transfer rate, a Delay-Locked Loop (DLL) or a Phase-Locked Loop (PLL) is used as an Input/Output (I/O) interface between chips in high-speed integrated circuits, such as DRAM, microprocessors, and communication chips.
In general, a delay-locked loop circuit is basically divided into two types: an analog delay-locked loop circuit and a digital delay-locked loop circuit depending on the type of feedback loop that controls the amount of delay.
The analog delay-locked loop circuit adopts a method of storing control information for controlling the amount of delay in the capacitor of a feedback loop. In general, the analog delay-locked loop circuit has a simple structure, the accurate delay control ability, and an excellent jitter characteristic. It is however difficult to easily apply the analog delay-locked loop circuit to various systems because the analog delay-locked loop circuit has low transplantation due to a characteristic sensitive to a change in the process of an analog circuit and sensitively responds to the noise of a control signal. Furthermore, it is difficult for the analog delay-locked loop circuit to have a wide operating frequency due to a long locking time and a non-linear characteristic of a voltage control delay line.
In contrast, the digital delay-locked loop circuit adopts a method of storing control information for controlling the amount of delay in digital bits through a limited state machine within a feedback loop. Accordingly, the digital delay-locked loop circuit has excellent transplantation to various systems and can support low power standby mode because it is resistant to the noise of a control signal and insensitive to a change of a digital block process. Furthermore, the digital delay-locked loop circuit may have a relatively rapid locking time and a wide operating frequency characteristic as compared with an analog method because it uses a digitally-controlled delay line. However, the digital delay-locked loop circuit may not precisely control delay because the digital delay-locked loop circuit uses discontinuous digital control information unlike the analog delay-locked loop circuit that uses continuous analog control information and thus it has low resolution of a controllable delay amount.
FIG. 1 is a signal diagram showing a locking algorithm which is commonly used in a delay-locked loop circuit.
Referring to FIG. 1, in the conventional delay-locked loop circuit, in order to synchronize the phases of an input clock signal INCLK and an output clock signal OUTCLK, the amount of delay time generated by an internal digitally-controlled delay line block must be at least one cycle tcycle or more of the input clock signal. Such a delay time is the most basic factor that limits the improvement of performance and availability of a delay-locked loop circuit that needs to implement a wide operating frequency range, high delay resolution, low power consumption, a small chip area, and high jitter performance.